module full_adder (
	input a, b, c0,
	output s, c1
);
	wire tmp1, tmp2, tmp3;
	half_adder ha1(
		.a(a),
		.b(b),
		.s(tmp1),
		.c(tmp2)
	);
	half_adder ha2 (
		.a(tmp1),
		.b(c0),
		.s(s),
		.c(tmp3)
	);
	assign c1 = tmp2 | tmp3;
endmodule
